It is desirable to convey data signals in a manner that provides relatively high speed while consuming relatively little power. Differential signaling modes such as low voltage differential signaling (LVDS) are used for many such applications. The rejection of common-mode noise inherent in a differential scheme allows for implementations having low power consumption, and the low voltage swing in an LVDS application allows for high-speed transmission. Moreover, drivers for such systems may be implemented in CMOS (complementary metal-oxide-semiconductor or “MOS”), which process provides low static power consumption.
Differential signaling circuits may be used to drive paired or unpaired transmission lines such as twisted pair cable, conductors in ribbon cable, or parallel traces on a circuit board. Differential signaling systems also tend to produce relatively little noise (electromagnetic interference or “EMI”) to interfere with other devices or signaling lines. Applications for differential signaling and LVDS include transmission of images (e.g. within a digital camera, or between a camera and a host), transmission of video images (e.g. from a host computer or processor to a display screen (such as within a laptop computer or a flat-panel display device), or over a distance of meters), and other high-speed transmissions of data (e.g. a high-speed disk storage interface).
In summary, a low voltage differential signaling scheme may provide numerous advantages such as reduced power consumption, lower EMI emissions, good rejection on common-mode noise, less expensive cable interface, and simplified transmitter design. FIG. 1 shows a structure of an LVDS input/output interface, which illustrates the low current, low termination impedance, and low voltage swing of such a scheme. Documents that define LVDS transmission schemes include the ANSI/TIA/EIA-644 standard, the IEEE 1596.3 standard (Scalable Coherent Interface LVDS or “SCI-LVDS”), and subsequent revisions thereof.
FIG. 2 shows one implementation of a LVDS driver circuit. In this circuit, N-channel MOS field-effect transistors (FETs) NP1, NP2, NS1, and NS2 are used to switch current through a load R1. In response to the input signals SN and SP changing signal states, these four transistors act as current-steering cells to switch the direction of a driving current (provided by current source CSR1) and offer a differential output signal to the resistive load. Current returning from the load is passed to current sink CSK1.
FIG. 3 shows a circuit including two digital inverters that may be used to generate input signals SN and SP for the circuit of FIG. 2 from a single digital signal.
FIG. 4 shows a diagram of the circuit of FIG. 2 that illustrates how the current source CSR1 and current sink CSK1 have actually been implemented previously (where CMC indicates a current mirroring circuit). In order to maintain a desired offset voltage, the driver circuit of FIG. 4 includes a mimicking circuit consisting of three regulating opamps (X1, X2, and X3); two series resistors R2, R3; and current sourcing and switching transistor cells PC1, NC1.
FIG. 5 shows an alternate LVDS driver circuit in which an offset voltage Voff is applied between a pair of series source-termination resistors R4, R5. FIG. 6 shows a circuit that may be used to generate analog differential signals to drive the circuit of FIG. 5, and FIG. 7 shows a diagram of the circuit of FIG. 5 that illustrates how the current source CSP and current sink CSN have actually been implemented previously, using a particular current mirror configuration.